`include "chunjun_define.sv" 
`include "chunjun_lib_define.sv" 

/*************************************************************************
    > File Name: lib_crg.sv
    > Created Time: Mon Sep  4 17:37:07 2023
 ************************************************************************/
module wing_cbb_icg_wrap (
    input  logic       clk        ,
    input  logic       clk_en     ,
    input  logic       scan_en    ,
    output logic       gated_clk 
);


// For simulation only.
// It should NOT be used for synthesis.

logic latch_en;
 
always_latch begin
    if (~clk) begin
        latch_en <= scan_en | clk_en;
    end
end

assign gated_clk = scan_en ? clk : (clk & latch_en);
 
 
endmodule

`include "chunjun_undefine.sv" 
